1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, for example, a NAND flash memory. In particular, the present invention relates to a semiconductor memory system including a plurality of built-in flash memories.
2. Description of the Related Art
A NAND flash memory requires the following threshold distribution within a limited threshold voltage range, for example, −2V to 5V. Specifically, if four values are given, four threshold distributions must be set. If eight values are given, eight threshold distributions must be set. If 16 values are given, 16 threshold distributions are set. In a write sequence, a program operation and a verify operation are made, and program voltage is gradually stepped up to repeat the program operation and the verify operation. As described above, the program voltage is gradually stepped up to repeat the program operation and the verify operation; for this reason, write time increases. As a result, write performance must be enhanced, and simultaneously, the number of write cells increases.
When the program operation is started, all bit lines must be charged. Moreover, when a verify read operation is started, all bit lines are charged to determine current carrying through all bit lines. Therefore, very large current is required, and thus, large peak current is temporarily generated.
The NAND flash memory is frequently used as the following multi-chip package (MCP) and memory card. The multi-chip package (MCP) has simultaneously some, for example, two to four built-in chips to increase storage capacity. The memory card has a plurality of built-in chips. As described above, when some chips are built in, if the peak current of each chip overlaps, larger peak current is generated. For this reason, there is a possibility of causing a problem such as disconnection reducing reliability.
In order to solve the foregoing problem, the following technique (e.g., see Jpn. Pat. Appln. KOKAI Publication No. 11-242632) has been developed. According to the technique, the peak value of current generated is reduced when write is concurrently made with respect to a plurality of chips. However, it is desired to prevent an increase of circuit configuration and securely and sufficiently reduce the peak current.